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6.1 Software – Transparente – Contactos – Navegador – Noticias Llicenas – comprar -. com.gerador.licena.aprouter.10.4.6./*
* zynq_sd.h
*
* Copyright (C) 2011-2012 Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __ZYNQ_SD_H
#define __ZYNQ_SD_H
/* SD Host Controller Base Address. */
#define ZYNQ_SD_BASE_ADDR 0xE000E000
/* Define SD host register base address */
#define SD_HSDRAM_EN_BASE 0x400
#define SD_HSDRAM_CS0_BASE 0x400
#define SD_HSDRAM_CS1_BASE 0xC000
#define SD_HSDRAM_CS2_BASE 0xC000
#define ZYNQ_SD_ALIVE_BASE 0xBF0
#define ZYNQ_SD_INTERNAL_VOLTAGE 0xB10
#define ZYNQ_SD_INTERNAL_PWR 0x10
#define SD_CMD_ACCESS_BASE 0x8400
#define SD_CMD_ACCESS2_BASE 0x8500
#define SD_CMD_HOST_CTRL_BASE 0x8800
#define SD_CMD_ADDR_BASE 0xA000
#define SD_CMD_DATA_BASE 0xA200
#define SD_DIP_1_VOLTAGE 0x32FC
#define SD_DIP_2_VOLTAGE 0xB32C
#define SD_DIP_3_VOLTAGE 0xC312
#define SD_DIP_4_VOLTAGE 0xD314
#define SD_CARD_VOLTAGE_CTL 0x8B10
#define SD_CARD_VOLTAGE_CTL
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Gerador Licena Aprouter 9.4 6 13.1.1.1 gerador licena aprouter 9.4 6. Gerador Licena Aprouter 9.4 6.1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device for adjusting the output voltage of a circuit.
2. Description of the Background Art
FIG. 7 is a circuit diagram showing the layout of a conventional semiconductor device for adjusting the output voltage of a circuit, to which the present invention is applied.
The semiconductor device for adjusting the output voltage of the circuit of FIG. 7 includes a bias voltage source 6, an offset current source 2, an NMOS transistor 1, and a diode 3. The bias voltage source 6 is connected between a power supply line 5 and the ground line 4. The offset current source 2 has an offset current source for supplying an offset current of the same magnitude as a current required to keep the collector potential of the NMOS transistor 1 constant. The NMOS transistor 1 has a collector connected to the power supply line 5, a base connected to the offset current source 2, and an emitter connected to the ground line 4. The diode 3 is connected between the base and emitter of the NMOS transistor 1 to supply a current from the base to the emitter. With the layout of FIG. 7, the diode 3 serves as a bootstrap circuit, in which the bias voltage source 6 is connected between the power supply line 5 and the emitter of the NMOS transistor 1.
A description will be given with reference to a semiconductor device A of FIG. 8 to semiconductor device B of FIG. 9.
FIG. 8 is a circuit diagram
