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How to Install Microsoft Office 365 Crack is a single-language open source application, developed by the .Metal-oxide semiconductor (MOS) device performance is often limited by the quality of the gate dielectric in the semiconductor substrate. The dielectric quality of silicon dioxide is often inadequate. Commonly known as “fixed charge,” charges trapped in the silicon dioxide gate dielectric tend to reduce threshold voltage of the MOS transistor, increase leakage currents and create interfacial states that adversely affect mobility of minority carriers. While a high-quality gate dielectric (compared to silicon dioxide) in the silicon may be obtained by recessing a portion of the gate dielectric, common methods used to create a recessed gate dielectric, such as a phosphoric-based anisotropic etch, often damage the underlying substrate.
In contrast, a technique known as “trench capacitance-voltage (CV) technique” uses a thinner gate dielectric in the substrate, i.e., the substrate is positioned between the gate dielectric and gate conductor. The trench for the thinner gate dielectric is filled with an oxide dielectric and top-surface oxidation of the substrate is removed to form a thinner gate dielectric at the substrate top-surface. Alternatively, prior art techniques have used oxide/nitride/oxide structures to form the trench. However, the extra interfaces between the dielectric structures often lead to higher defect densities. To avoid the extra interfaces, other prior art techniques form a stack of oxide/nitride/oxide layers. Each of these oxides must be thin enough so that the gate dielectric can be thinned to the desired thickness. However, these layers are often not conformal and are difficult to etch.
U.S. Pat. No. 4,293,719 discloses a method of fabricating trench capacitors. As seen in FIGS. 1A and 1B of the patent, the method of forming trench capacitors includes the step of forming a trench 20 in the surface of a substrate 10. The trench 20 is then lined with a dielectric 30 which has a thickness equal to a required capacitance of the trench capacitor. The dielectric is then oxidized to form a thin oxide layer 35. An upper portion of the thin oxide layer 35 is laterally recessed through a mask 40 to form a recess 45. The recess 45 can be at least 0.2 micron deep
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